The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device having a compression test mode.
As the fabrication technologies of semiconductor memory devices such as double data rate (DDR) synchronous dynamic random access memory (SDRAM) are rapidly advanced, the integration density of the semiconductor memory devices increases. Thus, ten millions of memory cells are integrated into a single semiconductor memory device. Due to the increase in the number of the memory cells, much more data can be stored. However, it takes a lot of time to test the memory cells. That is, a lot of test time is taken to determine pass/fail of ten millions of memory cells. The test time is an important factor in determining the product cost. Many attempts have been made to reduce the test time. One of them is a compression test method. The compression test method is to compress data stored in a plurality of memory cells. A test operator can determine whether the corresponding memory cell is normal or defective, based on the compressed data.
Meanwhile, a semiconductor memory device is designed to operate according to a data width option. The data width option is defined in a specification as an option that enables a user to set a desired data width. For example, if the data width option is set to “x8” in a semiconductor memory device having eight input/output pads, the data input/output operation is performed through the eight input/output pads. If the data width option is set to “x4”, the data input/output operation is performed through eight data input/output pads among the eight input/output pads.
The data width option may be set in a mode register set (MRS) provided in the semiconductor memory device. In addition to the data width option, a column address strobe (CAS) latency, a burst type, and a burst length may be set in the MRS. Information on additional operations may also be set in the MRS.
FIG. 1 is a block diagram of a conventional semiconductor memory device. A DDR2 SDRAM is exemplarily illustrated in FIG. 1. The DDR2 SDRAM includes eight banks of memory cells and eight input/output pads and can be set to x8 or x4 data width option. Also, since the DDR2 SDRAM uses a 4-bit prefetch scheme, each global input/output line includes four global input/output lines. That is, a first global input/output line GIO1 includes four global input/output lines GIO1<1>, GIO1<2>, GIO1<3> and GIO1<4>. For convenience, the four global input/output lines GIO1<1>, GIO1<2>, GIO1<3> and GIO1<4> are indicated by one global input/output line GIO1.
Referring to FIG. 1, the semiconductor memory device includes first to eighth banks. A row decoder/bank controller, a column decoder, and a write driver/read driver are provided in each bank. For convenience, a reference numeral “110B” is assigned to the row decoder/bank controller for the first bank 110A, and a reference numeral “110C” is assigned to the column decoder for the first bank 110A. Also, a reference numeral “110D” is assigned to the write driver/read driver for the first bank 110A.
The first to eighth banks are respectively selected by the bank controllers according to external bank addresses. Each of the first to eighth banks includes a plurality of memory cells. Specific memory cells of the selected banks are accessed by external row addresses and external column addresses. Therefore, data stored in the accessed memory cells are input/output through the first to eighth global input/output lines GIO1, GIO2, GIO3, GIO4, GIO5, GIO6, GIO7 and GIO8.
FIG. 2 is a circuit diagram illustrating a read operation and a write operation of a semiconductor memory device. In FIG. 2, a specific memory cell 210 among the plurality of memory cells included in the first bank 110A is illustrated as a representative.
The read operation of the semiconductor memory device will be described below with reference to FIGS. 1 and 2. Herein, description about a bank selection operation of the bank controller (see FIG. 1) will be omitted.
In the read operation, the row decoder (see FIG. 1) decodes a row address and enables a word line WL selected by the decoded row address. When the word lien WL is enabled, a cell transistor T1 of the memory cell 210 is turned on, and data stored in a cell capacitor C1 is charge-shared with precharged positive/negative bit lines BL and /BL. Due to the charge sharing operation, the positive/negative bit lines BL and /BL have a slight voltage difference. For reference, the precharge voltage has half the voltage level of an internal voltage, especially a core voltage.
A bit line sense amplifier 220 senses and amplifies the slight voltage difference between the positive bit line BL and the negative bit line /BL. When the voltage level of the positive bit line BL is higher than that of the negative bit line /BL, the voltage level of the positive bit line BL is amplified to a pull-up voltage level RTO, and the voltage level of the negative bit line /BL is amplified to a pull-down voltage level SB. On the other hand, when the voltage level of the positive bit line BL is lower than that of the negative bit line /BL, the voltage level of the positive bit line BL is amplified to a pull-down voltage level SB, and the voltage level of the negative bit line /BL is amplified to a pull-up voltage level RTO.
Meanwhile, the column decoder 110C decodes the column address and activates a corresponding column select signal YI. In response to the column select signal YI, the column selector 230 is enabled to connect the positive/negative bit lines BL and /BL to positive/negative segment input/output lines SIO and /SIO, respectively. That is, the amplified data on the positive bit line BL is transferred to the positive segment input/output line SIO, and the amplified data on the negative bit line /BL is transferred to the negative segment input/output line /SIO. Thereafter, when the input/output switching unit 240 is enabled in response to an input/output control signal CRT_IO, the positive/negative segment input/output lines SIO and /SIO are connected to positive/negative local input/output lines LIO and /LIO, respectively. That is, the data on the positive segment input/output line SIO is transferred to the positive local input/output line LIO, and the data on the negative segment input/output line /SIO is transferred to the negative local input/output line /LIO. The read driver 250 drives the first global input/output lien GIO1 according to the data transferred to the positive/negative local input/output lines LIO and /LIO.
Consequently, the data stored in the memory cell 210 are transferred to the first global input/output line GIO1 through the positive/negative bit lines BL and /BL, the positive/negative segment input/output lines SIO and /SIO, and the positive/negative local input/output lines LIO and /LIO.
Meanwhile, the external data input in a write operation is transferred in a direction opposite to the read operation. That is, the data is transferred from the first global input/output line GIO1 through the write driver 260 to the positive/negative local input/output lines LIO and /LIO, and then transferred through the positive/negative segment input/output lines SIO and /SIO to the positive/negative bit lines BL and /BL. The transferred data is finally stored in the memory cell 210.
For reference, RC loading caused by a plurality of resistors R and capacitors C illustrated in FIG. 2 is reflected on the data transferred through the respective lines.
The other blocks of the conventional semiconductor memory device will be described with reference to FIG. 1. First, the block associated with the read operation of the semiconductor memory device in the normal mode will be described. The description of the compression operation, that is, the first to fourth global compressors 170_1, 170_2, 170_3 and 170_4 and the compression test signal TPARA, will be described later with reference to FIG. 3.
The first to eighth global input/output lines GIO1, GIO2, GIO3, GIO4, GIO5, GIO6, GIO7 and GIO8 are input to the first to eighth output selectors 120_1, 120_2, 120_3, 120_4, 1205, 1206, 120_7 and 120_8. The first to eighth output selectors 120_1, 120_2, 120_3, 120_4, 120_5, 120_6, 120_7 and 120_8 output signals transferred through the first to eighth global input/output lines GIO1, GIO2, GIO3, GIO4, GIO5, GIO6, GIO7 and GIO8 in response to the selection signals IOx4 and CADD<11>.
The first to eighth global input/output lines GIO1, GIO2, GIO3, GIO4, GIO5, GIO6, GIO7 and GIO8 are connected to the first to eighth output selectors 1201, 1202, 1203, 1204, 1205, 1206, 120_7 and 120_8, respectively. In particular, the fifth to eighth global input/output lines GIO5, GIO6, GIO7 and GIO8 are further connected to the first to fourth output selectors 120_1, 120_2, 120_3 and 120_4 in order to execute the data width option. The selection signals include the data width option signal IOx4 and the line selection signal CADD<11>. The data width option signal IOx4 is a signal corresponding to the x4 data width option and the x8 data width option, and the line selection signal CADD<11> is a signal for selecting a desired one of the connected global input/output lines.
The first to fourth output selectors 120_1, 120_2, 120_3 and 120_4 or the fifth to eighth output selectors 120_5, 120_6, 120_7 and 120_8 are enabled in response to the data width option signal IOx4. When the first to fourth output selectors 120_1, 120_2, 120_3 and 120_4 are enabled, they output signals transferred through the global input/output lines selected in response to the line selection signal CADD<11>.
Meanwhile, first to eighth pipe latches 130_1, 130_2, 130_3, 130_4, 130_4, 130_5, 130_6, 130_7 and 130_8 latch output signals of the first to eighth output selectors 120_1, 120_2, 120_3, 120_4, 120_5, 120_6, 120_7 and 120_8, respectively. The output signals of the first to eighth output selectors 120_1, 120_2, 120_3, 120_4, 120_5, 120_6, 120_7 and 120_8 are output in parallel, and the first to eighth pipe latches 130_1, 130_2, 130_3, 130_4, 130_5, 130_6, 130_7 and 130_8 convert them into serial form.
The output signals of the first to eighth pipe latches 130_1, 130_2, 130_3, 130_4, 130_4, 130_5, 130_5, 130_6, 130_7 and 130_8 are output to the outside through the first to eighth input/output pads 140_1, 140_2, 140_3, 140_4, 1405, 1406, 140_7 and 140_8.
In other words, in the x8 data width option, the data corresponding to the first to eighth banks are input to the first to eighth output selectors 120_1, 120_2, 120_3, 120_4, 120_5, 120_6, 120_7 and 120_8 through the first to eighth global input/output lines GIO1, GIO2, GIO3, GIO4, GIO5, GIO6, GIO7 and GIO8. The output signals of the first to eighth output selectors 120_1, 120_2, 120_3, 120_4, 120_5, 120_6, 120_7 and 120_8 are latched in the first to eighth pipe latches 130_1, 130_2, 130_3, 130_4, 130_5, 130_6, 130_7 and 130_8 and output to the first to eighth input/output pads 140_1, 140_2, 140_3, 140_4, 140_5, 140_6, 140_7 and 140_8.
In the x4 data width option, the data corresponding to the first to fourth banks or the data stored in the fifth to eighth banks are input to the first to fourth output selectors 120_1, 120_2, 120_3 and 120_4 through the first to fourth global input/output lines GIO1, GIO2, GIO3 and GIO4 or the fifth to eighth global input/output lines GIO5, GIO6, GIO7 and GIO8. At this point, the first to fourth output selectors 120_1, 120_2, 120_3 and 120_4 are selected by the data width option signal IOx4. The first to fourth output selectors 120_1, 120_2, 120_3 and 120_4 output the signals transferred through the first to fourth global input/output lines GIO1, GIO2, GIO3 and GIO4 or the fifth to eighth global input/output lines GIO5, GIO6, GIO7 and GIO8 in response to the data width option signal IOx4 and the line selection signal CADD<11>. The transferred signals are latched in the first to fourth pipe latches 130_1, 130_2, 130_3 and 130_4 and output to the first to fourth input/output pads 140_1, 140_2, 140_3 and 140_4.
The blocks associated with the write operation of the semiconductor memory device in the normal mode will be described below.
The first to eighth input/output pads 140_1, 140_2, 140_3, 140_4, 140_5, 140_6, 140_7 and 140_8 receive serial data from the outside. First to eighth data aligners 150_1, 150_2, 150_3, 150_4, 150_5, 150_6, 150_7 and 150_8 align the serial data input through the first to eighth input/output pads 140_1, 140_2, 140_3, 140_4, 140_5, 140_6, 140_7 and 140_8 in parallel form.
First to eighth input selectors 160_1, 160_2, 160_3, 160_4, 160_5, 160_6, 160_7 and 160_8 output the output signals of the first to eighth data aligners 150_1, 150_2, 150_3, 150_4, 150_5, 150_6, 150_7 and 150_8 to the first to eighth global input/output lines GIO1, GIO2, GIO3, GIO4, GIO5, GIO6, GIO7 and GIO8 in response to the data width option signal IOx4 and the line selection signal CADD<11>. The data applied to the first to eighth global input/output lines GIO1, GIO2, GIO3, GIO4, GIO5, GIO6, GIO7 and GIO8 are stored in the first to eighth banks, respectively.
The write operation must also be performed according to the data width option. The first to fourth input selectors 160_1, 160_2, 160_3 and 160_4 or the fifth to eighth input selectors 1605, 1606, 160_7 and 160_8 are enabled in response to the data width option signal IOx4. When the first to fourth input selectors 160_1, 160_2, 160_3 and 160_4 are enabled, they output the output signals of the first to fourth data aligners 150_1, 150_2, 150_3 and 150_4 to the global input/output lines selected in response to the line selection signal CADD<11>.
In other words, in the case of the x8 data width option, the data input through the first to eighth input/output pads 140_1, 140_2, 140_3, 140_4, 140_5, 140_6, 140_7 and 140_8 are output as aligned data by the first to eighth data aligners 150_1, 150_2, 150_3, 150_4, 150_5, 150_6, 150_7 and 150_8. The aligned data are input to the first to eighth input selectors 160_1, 160_2, 160_3, 160_4, 160_5, 160_6, 160_7 and 160_8 and output through the first to eighth global input/output lines GIO1, GIO2, GIO3, GIO4, GIO5, GIO6, GIO7 and GIO8. Finally, the first to eighth banks store data input through the first to eighth global input/output lines GIO1, GIO2, GIO3, GIO4, GIO5, GIO6, GIO7 and GIO8.
In the case of the x4 data width option, the data input through the first to fourth input/output pads 140_1, 140_2, 140_3 and 140_4 are output as the aligned data by the first to fourth data aligners 150_1, 150_2, 150_3 and 150_4. At this point, the first to fourth input selectors 160_1 160_2, 160_3 and 160_4 are selected by the data width option signal IOx4, while the fifth to eighth input selectors 160_5, 160_6, 160_7 AND 160_8 are not selected. Therefore, the first to fourth input selectors 160_1, 160_2, 160_3 AND 160_4 output the aligned data through the first to fourth global input/output lines GIO1, GIO2, GIO3 and GIO4 or the fifth to eighth global input/output lines GIO5, GIO6, GIO7 and GIO8 in response to the data width option signal IOx4 and the line selection signal CADD<11>. The first to fourth banks or the fifth to eighth banks store the data transferred through the corresponding global input/output lines.
FIG. 3 is a block diagram for explaining the blocks associated with a compression operation of the semiconductor memory device. For convenience, new reference numerals are assigned to respective elements. A data compression unit 380 is further illustrated in a region where a column decoder 310C and a write driver/read driver 310D are disposed. For reference, since data are compressed in a compression test mode, only the first to fourth input/output pads 340_1, 340_2, 340_3 and 340_4 are needed.
First, the blocks associated with the data read operation in the compression test mode will be described below.
Data compressors 380 are provided in the first to eighth banks. The data compressors 380 compress data applied to sub global input/output lines IGIO<1:8> of the banks and output the compressed data through the global input/output lines. For convenience, the first bank 110A will be described as a representative example. The sub global input/output lines IGIO<1:8> transfer data stored in the eight memory cells corresponding to the first bank 110A. Since the first global input/output line GIO1 includes four global input/output lines GIO1<1:4>, 32 data are compressed and applied to the four global input/output lines GIO1<1:4>.
Meanwhile, first to fourth global compressors 370_1, 370_2, 370_3 and 370_4 compress data input through the global input/output lines connected thereto to generate first to fourth global compression data GIOSUM15, GIOSUM26, GIOSUM37 and GIOSUM48.
In other words, the first global compressor 370_1 compresses the data input through the first global input/output line GIO1 and the fifth global input/output line GIO5 to generate the first global compression data GIOSUM15. The second global compressor 370_2 compresses the data input through the second global input/output line GIO2 and the sixth global input/output line GIO6 to generate the second global compression data GIOSUM26. The third global compressor 370_3 compresses the data input through the third global input/output line GIO3 and the seventh global input/output line GIO7 to generate the third global compression data GIOSUM37. The fourth global compressor 370_4 compresses the data input through the fourth global input/output line GIO4 and the eighth global input/output line GIO8 to generate the fourth global compression data GIOSUM48.
The first to fourth global compression data GIOSUM15, GIOSUM 26, GIOSUM37 and GIOSUM48 are input to the first to fourth output selectors 320_1, 320_2, 320_3 and 320_4, respectively. The first to fourth output selectors 320_1, 320_2, 320_3 and 320_4 output the first to fourth global compression data GIOSUM15, GIOSUM26, GIOSUM37 and GIOSUM48 to the first to fourth pipe latches 330_1, 330_2, 330_3 and 340_4 in response to the compression test signal TPARA. The first to fourth pipe latches 330_1, 330_2, 330_3 and 330_4 latch and output the first to fourth global compression data GIOSUM15, GIOSUM26, GIOSUM37 and GIOSUM48 to the first to fourth input/output pads 340_1, 340_2, 340_3 and 340_4. The first to fourth global compression data GIOSUM15, GIOSUM26, GIOSUM37 and GIOSUM48 are output to the outside through the first to fourth input/output pads 340_1, 340_2, 340_3 and 340_4. The compression test signal TPARA is a signal that is activated in a compression test mode for a compression test.
The blocks associated with the data write operation in the compression test mode will be described below.
The data input through the first to fourth input/output pads 340_1, 340_2, 340_3 and 340_4 are aligned by the first to fourth data aligners 350_1, 350_2, 350_3 and 350_4 and input to the first to fourth input selectors 360_1, 360_2, 360_3 and 360_4. The first to fourth input selectors 360_1, 360_2, 360_3 and 360_4 output the data to the global input/output lines in response to the compression test signal TPARA. That is, the first input selector 360_1 outputs the data to the first and fifth global input/output lines GIO1 and GIO5; the second input selector 360_2 outputs the data to the second and sixth global input/output lines GIO2 and GIO6; the third input selector 360_3 outputs the data to the third and seventh global input/output lines GIO3 and GIO7; and the fourth input selector 360_4 outputs the data to the fourth and eighth global input/output lines GIO4 and GIO8. Thereafter, the data transferred through the first to eighth global input/output lines GIO1, GIO2, GIO3, GIO4, GIO5, GIO6, GIO7 and GIO8 are stored in the first to eighth banks, respectively.
As described above, in the compression test mode, the conventional semiconductor memory device stores the data in the banks by using the four input/output pads, and outputs the compressed data by using the four input/output pads. When storing the data in the banks by using the four input/output pads, the test operator must apply the data to be stored in the banks to the respective input/output pads. In addition, since a test apparatus having finite test pins must allocate four test pins per the semiconductor memory device, there is a limitation in the number of semiconductor memory devices that can be tested at a time.